1. Technical Field
The present disclosure relates to a gate drive circuit where the output current of an output transistor, which drives a switching element on/off, can be kept constant despite temperature or supply voltage fluctuations.
2. Description of Related Art
A gate drive circuit which drives a switching element on/off, such as an insulated gate bipolar transistor (IGBT) or metal-oxide-semiconductor field-effect-transistor (MOS-FET), in a power converter is configured in such a way as in, for example, FIG. 6. In FIGS. 6, Q1 and Q2 are switching elements, each formed of a MOS-FET forming a half-bridge circuit, and gate drive circuit 1 drives the high-side switching element Q1 on/off. A gate drive circuit 2 which drives the low-side switching element Q2 on/off is also configured in the same way as the gate drive circuit 1. Consequently, herein, a description will be given of the gate drive circuit 1, which drives the high-side switching element Q1.
The gate drive circuit 1 includes an output transistor PM2, formed of a p-channel MOS-FET, which supplies a constant current to the gate of the switching element Q1 and drives the switching element Q1 on/off. Furthermore, the gate drive circuit 1 includes an output transistor NM2, formed of an n-channel MOS-FET connected in totem-pole fashion to the output transistor PM2, which is controlled on/off in a complementary relationship with the output transistor PM2.
Also, the gate drive circuit 1 includes a transistor PM1, formed of a p-channel MOS-FET, which configures a current mirror circuit with the output transistor PM2. Furthermore, the gate drive circuit 1 includes a control transistor NM1, formed of an n-channel MOS-FET. A current Icont, of which, is controlled by the output of an error amplifier AMP with the transistor PM1 as a load. Incidentally, the error amplifier AMP assumes the role of making the current Icont constant in response to a voltage difference between a voltage, at resistor R1 in response to the current Icont flowing through the control transistor NM1, and a reference voltage Vref.
Also, a transistor NM3, which is formed of an n-channel MOS-FET and is driven on/off in response to a gate control signal nDRV, controls the on/off drive of the control transistor NM1 by the output of the error amplifier AMP. When control transistor NM1 turns on, the current Icont flowing through the control transistor NM1 flows via the transistor PM1. As a result, a current proportional to the current Icont flows through the output transistor PM2 configuring the current mirror circuit with the transistor PM1. The current is supplied to the gate of the switching element Q1, and the switching element Q1 is driven on.
That is, the gate drive circuit 1 of the described configuration, in accordance with the constant current Icont generated by the error amplifier AMP and control transistor NM1, controls the on-current of the output transistor PM2 via the transistor PM1. Further, the gate drive circuit 1, under the current control, drives the switching element Q1 on with the constant current. Consequently, the time to charge the gate capacitance of the switching element Q1 is made constant despite temperature or supply voltage fluctuations. As a result, the turn-on time of the switching element Q1 is kept constant.
Also, FIG. 7 shows a gate drive circuit introduced in JP-A-2010-193431. The gate drive circuit 3 is configured in such a way as to control on/off of an output transistor 4, which is formed of a p-channel MOS-FET and drives the switching element Q1 on/off, using a pre-driver 7 of a complementary metal-oxide-semiconductor (CMOS) configuration formed of a p-channel MOS-FET 5 and n-channel MOS-FET 6. Further, the source voltage which is the operating reference voltage of the n-channel MOS-FET 6 in the pre-driver 7 is defined by a constant voltage source 8, thereby driving the switching element Q1 with a constant voltage Vg1.